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GD25LQ40 datasheet http://www.elm-tech.com
2 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash - content - page 1. f eatures --------------------------- --------------------------- ---------------------------- - -------------- 4 2. general description ------------------------------------------------------ - ---------------------- 5 3. memory organization --------------------------------------------------------- - ---------------- 6 4. device operation ----------------------------------------------------------------- - - - - - - - - - ------ - - 7 5. data protection ----------------------------------------------------------------------- - - - - - ------- - 8 6. status register -------------------------------------------------------------- - - - - - - - - - - - - - - - ------- - 10 7. commands description ------------------------------------------- --- - - - - - - - - - - - - - - - - - --------- - 1 1 7.1. write enable (wren) (06h) ---------------------------------------------------- - - - - - - - - - - - - ------- 1 5 7.2. write disable (wrdi) (04h) ------------------------------------------------------------- - - - - - - - - - - 1 6 7.3. write enable for volatile status register (50h) ---------- ---------- -------------- ------- ----- - - -- 1 7 7.4. read status register (rdsr) (05h or 35h) --------------------------------------------- - ------- - 1 8 7.5. write status register (wrsr) (01h) -------------------------------------------------- - - - - - - ------ 1 9 7.6. read data bytes (read) (03h) ------------------------------------------------ - - - - - - - - - - - - - ------- 20 7.7. read data bytes at higher speed (fast read) (0bh) ---------------------- - - - - - - - - - - - - - - ------- 20 7.8. dual output fast read (3bh) --------------------------------------------------------- - - - - - - - ------ 21 7.9. quad output fast read (6bh) ------------------------------------------------------ - --------------- 2 2 7.10. dual i/o fast read (bbh) ------------------------------------------------------------------ - - - - --- - 2 2 7.11. quad i/o fast read (ebh) -------------------------------------------------------------- - - - - - - ---- - - 2 3 7.12. quad i/o word fast read (e7h) ------------------------------------------------------------------ 2 5 7. 1 3 . set burst with wrap (77h) ---------------------------------------------------------------- - - - - - - --- - 2 7 7.14. page program (pp) (02h) - -------------------------------------------------------------------------- - 2 7 7.15. quad page program (32h) - ------------ -------------- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --- ------- 2 9 7.16. sector erase (se) (20h) ---------- ------------------------------------------------ - - - - - - - - - - - - ------- 30 7.17. 32kb block erase (be) (52h) --------------------------------------------------------------------- 31 7.18. 64kb block erase (be) (d8h) ------------------------------------------------------ - - - - - - - - - ------ 3 2 7.19. chip erase (ce) (60/c7h) ---------- ---------------- -------------- ------- --- --- --- --- --- - - - - - - - - - --- 3 3 7.2 0 . deep power-down (dp) (b9h) ---------------------------------------------------------------- - --- - 3 4 7.21. release from deep power-down and read device id (rdi) (abh) ------------------------ - 3 5 7.22. read manufacture id/device id (rems) (90h) ---------- -------- -------------- - --- ----- - ------- 3 7 7.23. read manufacture id/device id dual i/o (92h) ---------- -------- ----- -- --- --- --- -- - - --- - ------ 3 8 7.24. read manufacture id/device id quad i/o (94h) ---- -- -------------- ------- --- --- - - -- --- --- ---- 39 7. 25 . read identification (rdid) (9fh) ------------------------------------------------------------- - --- - 4 0 7.26. program/erase suspend (pes) (75h) ---- ----------------------------- --- --- --- --- --- ---- ---------- 4 1 7. 27 . program/erase resume (per) (7ah) --------------------------------------------------------- - --- - 4 2
3 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7.28. erase security registers (44h) -------------------------------- ------------------------------- ------- 4 3 7.29. program security registers (42h) ---------------------------------- ------- ------- ------- ---- ------- 4 4 7.30. read security registers (48h) -------------------------------- ------ ------ ------ ------ ------ -------- 4 5 7.31. set read parameters (c0h) ----- -------- ------------------- --- ------ ------ ------ ------ ------ -------- 4 6 7.32. bu rst read with wrap (0ch) ----- ------- ------------------- --- ------ ------ ------ ------ ------ ------- 4 7 7.33. enable qpi (38h) ----- ------- - ------------------ --- ------ ------ --------- -------- ------- ------ -------- 4 7 7.34. d isable qpi (ffh) ----- ------ - - - ------------------ --- ------ ------ ----------- -------- --- ------ -------- 4 8 7. 35 . enable reset (66h) and reset (99h) --------------------------------------------------------- - - --- - 49 8 . electrical characteristics ------------------------------------------- - ------------------- 5 0 8 .1. power- on timing ------------------------------------------------------------------------------------- 5 0 8 .2. initial delivery state ---------------------------------------------------------------------------------- 5 0 8 .3. data retention and endurance ----------------------------------------------------------------------- 5 0 8 .4. latch up characteristics ----------------------------------------------------------------------------- 5 0 8 .5. abso lute maximum ratings ------------------------------------------------------------------------- 5 1 8 .6 . capacitance measurement co nditions -------------------------------------------------------- - --- - 5 1 8 .7. dc characteristics ----------------------------------------------------------------------------------- 5 2 8 .8. a c characteristics --------------------------------------------------------------------------- -------- 5 3 9 . ordering information --------------------------------------------------- --------------------- - 5 5 10 . package information ------------------------------------------- ------------------------------- - 5 6 10 .1. package sop8 150mil ------------------------------------------------ ------------------ ----------- 5 6 10 .2. package sop8 208mil ----------------------------------------------- ------------------ -------- ---- 5 7 10.3. package uson8 (4x3mm) ---------------------------------------------------------- - - ------------ 5 8 10.4. package w son8 (6x5mm) ---------------------------------------------------------- - - - ---- ------- 59
4 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 1. features ? 4 m-bit serial flash - 512k-byte - 256 bytes per programmable page ? standard, dual, quad spi, qpi - standard spi: sclk, cs#, si, so, wp#, hold# - dual spi: sclk, cs#, io0, io1, wp#, hold# - quad spi: sclk, cs#, io0, io1, io2, io 3 - qpi: sclk, cs#, io0, io1, io2, io 3 ? high speed clock frequency - 120mhz for fast read with 30pf load - dual i/o data transfer up to 240mbits/s - quad i/o data transfer up to 480mbits/s - qpi mode data transfer up to 480mbits/s - continuous read with 8/16/32/64-byte wrap ? software/hardware write protection - w rite protect all/portion of memory via software - enable/disable protection with wp# pin - top or bottom, sector or block selection ? minimum 100,000 program/erase cycles ? program/erase speed - page program time: 0.4ms typical - sector erase time: 60ms typical - block e rase time: 0.3/0.5s typical - chip e rase time: 4s typical ? flexible architecture - sector of 4k-byte - block of 32/64k-byte - erase/program suspend/resume ? low power consumption - 2 0 ma maximum active current - 5a maximum power down current ? advanced security features - 4*256-byte security registers with otp lock ? single power supply voltage - full voltage range: 1.65~1.95v http://www.elm-tech.com
5 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash http://www.elm-tech.com 2. general description the GD25LQ40 (4m-bit) serial flash supports the standard serial peripheral interface (spi), and supports the dual/quad spi and qpi mode: serial clock, chip select, serial data i/o0 (si), i/o1 (so), i/o2 (wp#), and i/o3 (hold#). the dual i/o data is transferred with speed of 240mbits/s and the quad i/o & quad output data is transferred with speed of 480mbits/s. 8-lead sop 8-lead uso n/wson pin name i/o description cs# i chip select input so (io1) i/o data output (data input output 1) wp# (io2) i/o write protect input (data input output 2) vss ground si (io0) i/o data input (data input output 0) sclk i serial clock input hold# (io3) i/o hold input (data input output 3) vcc power supply pin description spi command & control logic high voltage generators page address latch / counter status register write control logic byte address latch / counter column decode and 256 - byte page buffer write protect logic and row decode flash memory cs # sclk si( io 0) so( io 1) hold #( io 3) wp #( io 2) block diagram connection diagram
6 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash each device has each block has each sector has each page has 512 k 64/32k 4k 256 bytes 2 k 256/128 16 - pages 128 16/8 - - sectors 8 /16 - - - blocks 3. memory organization uniform block sector architecture block sector address range 7 127 07f000h 07ffffh ----- ----- ----- 112 070000h 070fffh 6 111 06f000h 06ffffh ----- ----- ----- 96 060000h 060fffh ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- 2 47 02f000h 02ffffh ----- ----- ----- 32 020000h 020fffh 1 31 01f000h 01ffffh ----- ----- ----- 16 010000h 010fffh 0 15 00f000h 00ffffh ----- ----- ----- 0 000000h 000fffh GD25LQ40 GD25LQ40 64k bytes block sector architecture
7 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 4 . device operation spi mode standard spi the GD25LQ40 feature a serial peripheral interface on 4 signals bus: serial clock (sclk), chip select (cs#), serial data input (si) and serial data output (so). both spi bus mode 0 and 3 are supported. input data is latched on the rising edge of sclk and data shifts out on the falling edge of sclk. dual spi the GD25LQ40 supports dual spi operation when using the dual output fast read and dual i/o fast read (3bh and bbh) commands. these commands allow data to be transferred to or from the device at two times the rate of the standard spi. when using the dual spi command the si and so pins become bidirectional i/o pins: io0 and io1. quad spi the GD25LQ40 supports quad spi operation when using the quad output fast read, quad i/o fast read, quad i/o word fast read (6bh, ebh, e7h) commands. these commands allow data to be transferred to or from the device at four times the rate of the standard spi. when using the quad spi command the si and so pins become bidirectional i/o pins: io0 and io1, and wp# and hold# pins become io2 and io3. quad spi commands require the non-volatile quad enable bit (qe) in status register to be set. qpi the GD25LQ40 supports quad peripheral interface (qpi) operations only when the device is switched ftom standard/dual/quad spi mode to qpi mode using the enable the qpi (38h) command. the qpi mode utilizes all four io pins to input the command code. standard/dual/quad spi mode and qpi mode are exclusive. only one mode can be active at any given times. enable the qpi (38h) and disable the qpi (ffh) commands are used to switch between these two modes. upon power-up and after software reset using reset (99h) command, the default state of the device is standard/dual/quad spi mode. the qpi mode requires the non-volatile quad enable bit (qe) in status register to be set. hold the hold# signal goes low to stop any serial communications with the device, but doesnt stop the operation of write status register, programming, or erasing in progress. the operation of hold, need cs# keep low, and starts on falling edge of the hold# signal, with sclk signal being low (if sclk is not being low, hold operation will not start until sclk being low). the hold condition ends on rising edge of hold# signal with sclk being low (if sclk is not being low, hold operation will not end until sclk being low). the so is high impedance, both si and sclk dont care during the hold operation, if cs# drives high during hold operation, it will reset the internal logic of the device. to re-start communication with chip, the hold# must be at high and then cs# must be at low.
8 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash status register content memory content bp4 bp3 bp2 bp1 bp0 blocks addresses density portion 0 0 0 none none none none 0 0 0 0 1 7 070000h-07ffffh 64 kb upper 1/8 0 0 0 1 0 6 and 7 060000h-07ffffh 128 kb upper 1/4 0 0 0 1 1 4 to 7 0 4 0000h-07ffffh 256 kb upper 1/2 0 1 0 0 1 0 0 00000h-00ffffh 64 k b lower 1/8 0 1 0 1 0 0 and 1 0 00000h-01ffffh 128 k b lower 1/ 4 0 1 0 1 1 0 to 3 0 00 000h-03ffffh 256kb lower 1/ 2 0 1 0 to 7 0 00 000h-07ffffh 512 kb all 1 0 0 0 1 7 0 7 f 000h-07ffffh 4 kb upper 1/128 1 0 0 1 0 7 07e000h- 07ffffh 8 kb upper 1/ 64 1 0 0 1 1 7 07c000h- 07ffffh 16 k b upper 1/ 32 1 0 1 0 7 078000h- 07ffffh 32kb upper 1/ 16 1 0 1 1 0 7 078000h-07ffffh 32 kb upper 1/1 6 1 1 0 0 1 0 000000h-000fffh 4 kb lower 1/128 1 1 0 1 0 0 000000h-001fffh 8 kb lower 1/ 64 1 1 0 1 1 0 000000h-003fffh 16kb lower 1/ 32 1 1 1 0 0 000000h-007fffh 32kb lower 1/ 16 1 1 1 1 0 0 000000h-007fffh 32kb lower 1/ 16 1 1 1 1 0 to 7 000000h-07ffffh 512 kb all table 1. GD25LQ40 protected area size (cmp=0) 5 . data protection the GD25LQ40 provides the following data protection methods: ? write enable (wren) command: the wren command is set the write enable latch bit (wel). the wel bit will return to reset by the following situation: - power-up / write disable (wrdi) / write status register (wrsr) - page program (pp) / sector erase (se) / block erase (be) / chip erase (ce) ? software protection mode: the block protect (bp4, bp3, bp2, bp1, bp0) bits define the section of the memory array that can be read but not change. ? hardware protection mode: wp# going low to protected the bp0~bp4 bits and srp0~1 bits. ? deep power-down mode: in deep power-down mode, all commands are ignored except the release from deep power-down mode command. figure 1. hold condition hold hold cs # sclk hold #
9 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash status register content memory content bp4 bp3 bp2 bp1 bp0 blocks addresses density portion 0 0 0 0 to 7 000000h-07ffffh 512kb all 0 0 0 0 1 0 to 6 000000h-06ffffh 448 kb lower 7/ 8 0 0 0 1 0 0 to 5 000000h-05ffffh 384 kb lower 3/ 4 0 0 0 1 1 0 to 3 000000h-03ffffh 256 kb lower 1/ 2 0 1 0 0 1 1 to 7 010000h-07ffffh 448 k b upper 7 / 8 0 1 0 1 0 2 to 7 020000h-07ffffh 384 k b upper 3/ 4 0 1 0 1 1 4 to 7 040000h-07ffffh 256k b upp er 1/ 2 0 1 none none none none 1 0 0 0 1 0 to 7 000000h-07efffh 508 kb lower 127/128 1 0 0 1 0 0 to 7 000000h-07dfffh 504 kb lower 63/ 64 1 0 0 1 1 0 to 7 000000h-07bfffh 496 kb lower 31/ 32 1 0 1 0 0 to 7 000000h-077fffh 480 kb lower 15/1 6 1 0 1 1 0 0 to 7 000000h-077fffh 480 kb lower 15/1 6 1 1 0 0 1 0 to 7 001000h-07ffffh 508 kb upper 127/128 1 1 0 1 0 0 to 7 002000h-07ffffh 504 kb upper 63/ 64 1 1 0 1 1 0 to 7 004000h-07ffffh 496 kb upper 31/ 32 1 1 1 0 0 to 7 008000h-07ffffh 480 kb upper 15/ 16 1 1 1 1 0 0 to 7 008000h-07ffffh 480 kb upper 15/ 16 1 1 1 1 none none none none table 1a. GD25LQ40 protected area size (cmp=1)
10 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 6 . status register the status and control bits of the status register are as fo llows: w ip bit. the write in progress (wip) bit indicates whether the memory is busy in program/erase/write status register progress. when wip bit sets to 1, means the device is busy in program/erase/write status register progress, when wip bit sets 0, means the device is not in program/erase/write status register progress. wel bit. the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write status register, program or erase command is accepted. bp4, bp3, bp2, bp1, bp 0 bits. the block protect (bp4, bp3, bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase commands. these bits are written with the write status register (wrsr) command. when the block protect (bp4, bp3, bp2, bp1, bp0) bits are set to 1, the relevant memory area (as defined in table1). becomes protected against page program (pp), sector erase (se) and block erase (be) commands. the block protect (bp4, bp3, bp2, bp1 and bp0) bits can be written provided that the hardware protected mode has not been set. the chip erase (ce) command is executed, only if the block protect (bp4, bp3, bp2, bp1 and bp0) are set to none protected. srp1, srp0 bits. the status register protect (srp1 and srp0) bits are non-volatile read/write bits in the status register. the srp bits control the method of write protection: software protection, hardware protection, power supply lock- down or one time programmable protection. s15 s14 s13 s12 s11 s10 s9 s8 sus1 cmp lb3 lb2 lb1 sus2 qe srp1 s7 s6 s5 s4 s3 s2 s1 s0 srp0 bp4 bp3 bp2 bp1 bp0 wel wip srp1 srp 0 #wp status register description 0 0 software protected the status register can be written to after a write enable command, wel=1.(default) 0 1 0 hardware protected wp# = 0, the status register locked and can not be written to. 0 1 1 hardware unprotected wp# = 1, the status register is unlocked and can be written to after a write enable command, wel=1. 1 0 power supply lock-down(1) status register is protected and can not be written to again until the next power-down, power-up cycle. 1 1 one time program(1) status register is permanently protected and can not be written to. note: (1). when srp1, srp0= (1, 0), a power-down, power-up cycle will change srp1, srp0 to (0, 0) state.
11 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash qe bit. the quad enable (qe) bit is a non-volatile read/write bit in the status register that allows quad operation. when the qe bit is set to 0 (default) the wp# pin and hold# pin are enable. when the qe pin is set to 1, the quad io2 and io3 pins are enabled. (the qe bit should never be set to 1 during standard spi or dual spi operation if the wp# or hold# pins are tied directly to the power supply or ground). lb3, lb2, lb1 bits. the lb3, lb2, lb1 bits are non-volatile one time program (otp) bits in status register (s13-s11) that provide the write protect control and status to the security registers. the default state of lb3-lb1 are 0, the security registers are unlocked. the lb3-lb1 bits can be set to 1 individually using the write register instruction. the lb3-lb1 bits are one time programmable, once its set to 1, the security registers will become read-only permanently. cmp bit. the cmp bit is a non-volatile read/write bit in the status register (s14). it is used in conjunction the bp4- bp0 bits to provide more flexibility for the array protection. please see the status registers memory protection table for details. the default setting is cmp=0. sus1, sus2 bits. the sus1 and sus2 bits are read only bit in the status register (s15 and s10) that are set to 1 after executing an program/ erase suspend (75h) command (the erase suspend will set the sus1 to 1, and the program suspend will set the sus2 to 1) . the sus1 and sus2 bits are cleared to 0 by program/ erase resume (7ah) command as well as a power-down, power-up cycle. 7. commands description all commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of sclk after cs# is driven low. then, the one-byte command code must be shifted in to the device, most significant bit first on si, each bit being latched on the rising edges of sclk. see table2, every command sequence starts with a one-byte command code. depending on the command, this might be followed by address bytes, or by data bytes, or by both or none. cs# must be driven high after the last bit of the command sequence has been shifted in. for the command of read, fast read, read status register or release from deep power-down, and read device id, the shifted-in command sequence is followed by a data- out sequence. cs# can be driven high after any bit of the data-out sequence is being shifted out. for the command of page program, sector erase, block erase, chip erase, write status register, write enable, write disable or deep power-down command, cs# must be driven high exactly at a byte boundary, otherwise the command is rejected, and is not executed. that is cs# must driven high when the number of clock pulses after cs# being driven low is an exact multiple of eight. for page program, if at any time the input byte is not a full byte, nothing will happen and wel will not be reset.
12 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash command name byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 n-bytes write enable 06h write disable 04h volatile sr write enable 50h read status register 05h (s7-s0) (continuous) read status register-1 3 5h (s15-s8) (continuous) write status register 01h (s7-s0) (s15-s8) read data 03h a23-a16 a15-a8 a7-a0 (d7-d0) (next byte) (continuous) fast read 0bh a23-a16 a15-a8 a7-a0 dummy (d7-d0) (continuous) dual output fast read 3bh a23-a16 a15-a8 a7-a0 dummy d7-d0 (1) (continuous) dual i/o fast read bbh a23 -a8 (2) a7-a0 m7 -m0 (2) (d7-d0) (1) (continuous) quad output fast read 6bh a23-a16 a15-a8 a7-a0 dummy (d7 -d0) (3) (continuous) quad i/o fast read ebh a23-a0 m7 -m0 (4) dummy (5) (d7-d0) (3) (continuous) quad i/o word fast read (7) e7h a23-a0 m7 -m0 (4) dummy (6) (d7-d0) (3) (continuous) page program 02h a23-a16 a15-a8 a7-a0 (d7-d0) next byte quad page program 32h a23-a16 a15-a8 a7-a0 (d7-d0) (3) sector erase 20h a23-a16 a15-a8 a7-a0 block erase (32k) 52h a23-a16 a15-a8 a7-a0 block erase (64k) d8h a23-a16 a15-a8 a7-a0 chip erase c7/60h enable qpi 38h enable reset 66h reset 99h set burst with wrap 77h w6-w 4 program/erase suspend 75h program/erase resume 7ah deep power-down b9h release from deep power-down, and read device id abh dummy dummy dummy (id7-id0) (continuous) release from deep power-down abh manufacturer/device id 90h dummy dummy 00h (m7- m0) (id7-id0) (continuous) manufacturer/device id by dual i/o 92h a23-a8 a7-a0, m[7:0] (m7-m0) (id7-id0) (continuous) manufacturer/device id by quad i/o 94h a23-a0, m[7:0] dumm y (m7-m0) (id7-id0) (continuous) read identification 9fh (m7-m0) (id15- id8) (id7- id0) (continuous) erase security registers (8) 44h a23-a16 a15-a8 a7-a0 program security registers (8) 42h a23-a16 a15-a8 a7-a0 (d7-d0) (d7-d0) read security registers (8) 48h a23-a16 a15-a8 a7-a0 dummy (d7-d0) table 2. commands (standard/dual/quad spi)
13 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash command name byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 clock number (0, 1) (2, 3) (4, 5) (6, 7) (8, 9) (10, 11) write enable 06h volatile sr write enable 50h write disable 04h read status register 05h (s7-s0) read status register-1 3 5h (s15-s8) write status register 01h (s7-s0) (s15-s8) page program 02h a23-a16 a15-a8 a7-a0 (d7-d0) next byte sector erase 20h a23-a16 a15-a8 a7-a0 block erase (32k) 52h a23-a16 a15-a8 a7-a0 block erase (64k) d8h a23-a16 a15-a8 a7-a0 chip erase c7/60h program/erase suspend 75h program/erase resume 7ah deep power-down b9h set read parameters c0 h p7-p0 fast read 0bh a23-a16 a15-a8 a7-a0 dummy (d7-d0) burst read with wrap 0ch a23-a16 a15-a8 a7-a0 dummy (d7-d0) quad i/o fast read eb h a23-a16 a15-a8 a7-a0 m7-m0 (d7-d0) release from deep power-down, and read device id abh dummy dummy dummy (id7- id0) manufacturer/device id 90h dummy dummy 00h (m7- m0) (id7-id0) read identification 9fh (m7-m0) (id15- id8) (id7- id0) disable qpi ff h enable reset 66h reset 99h table 2a. commands (qpi) note: (1) dual output data io0 = (d6, d4, d2, d0) io1 = (d7, d5, d3, d1) (2) dual input address io0 = a22, a20, a18, a16, a14, a12, a10, a8 a6, a4, a2, a0, m6, m4, m2, m0 io1 = a23, a21, a19, a17, a15, a13, a11, a9 a7, a5, a3, a1, m7, m5, m3, m1 (3) quad output data io0 = (d4, d0, ..) io1 = (d5, d1, ..) io2 = (d6, d2, ..) io3 = (d7, d3,..)
14 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash (4) quad input address io0 = a20, a16, a12, a8, a4, a0, m4, m0 io1 = a21, a17, a13, a9, a5, a1, m5, m1 io2 = a22, a18, a14, a10, a6, a2, m6, m2 io3 = a23, a19, a15, a11, a7, a3, m7, m3 (5) fast read quad i/o data io0 = (x, x, x, x, d4, d0,) io1 = (x, x, x, x, d5, d1,) io2 = (x, x, x, x, d6, d2,) io3 = (x, x, x, x, d7, d3,) (6) fast word read quad i/o data io0 = (x, x, d4, d0,) io1 = (x, x, d5, d1,) io2 = (x, x, d6, d2,) io3 = (x, x, d7, d3,) (7) fast word read quad i/o data: the lowest address bit must be 0. (8) security registers address: security register0: a23-a16=00h, a15-a8=00h, a7-a0=byte address; security register1: a23-a16=00h, a15-a8=10h, a7-a0=byte address; security register2: a23-a16=00h, a15-a8=20h, a7-a0=byte address; security register3: a23-a16=00h, a15-a8=30h, a7-a0=byte address . (9) qpi command, address, data input/output format: clk #0 1 2 3 4 5 6 7 8 9 10 11 io0 = c4, c0, a20, a16, a12, a8, a4, a0, d4, d0, d4, d0 io1 = c5, c1, a21, a17, a13, a9, a5, a1, d5, d1, d5, d1 io2 = c6, c2, a22, a18, a14, a10, a6, a2, d6, d2, d6, d2 io3 = c7, c3, a23, a19, a15, a11, a7, a3, d7, d3, d7, d3 table of id definitions: gd25lq4 0 operation code m7-m0 id15-id8 id7-id0 9fh c8 6 0 13 90h c8 12 abh 12
15 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7.1 . write enable (wren)(06h) the write enable (wren) command is for setting the write enable latch (wel) bit. the write enable latch (wel) bit must be set prior to every page program (pp), sector erase (se), block erase (be), chip erase (ce), write status register (wrsr) and erase/program security registers command. the write enable (wren) command sequence: cs# goes low sending the write enable command cs# goes high. command 0 1 2 3 4 5 6 7 06h cs# sclk si so high-z figure 2. write enable sequence diagram cs # sclk io 0 io 1 io 2 io 3 0 1 command 06 h figure 2a. write enable sequence diagram (qpi)
16 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash cs # sclk io 0 io 1 io 2 io 3 0 1 command 04 h figure 3a. write disable sequence diagram (qpi) 7.2. write disable (wrdi) (04h) the write disable command is for resetting the write enable latch (wel) bit. the write disable command sequence: cs# goes low sending the write disable command cs# goes high. the wel bit is reset by following condition: power-up and upon completion of the write status register, page program, sector erase, block erase, chip erase, erase/ program security registers and reset commands. command 0 1 2 3 4 5 6 7 04h cs# sclk si so high-z figure 3. write disable sequence diagram
17 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash figure 4. write enable for volatile status register sequence diagram cs# sclk command(50h) si so 0 1 2 3 4 5 6 7 high -z 7.3 . write enable for volatile status register (50h) the non-volatile status register bits can also be written to as volatile bits. this gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non- volatile bit write cycles or affecting the endurance of the status register non-volatile bits. the write enable for volatile status register command must be issued prior to a write status register command. the write enable for volatile status register command will not set the write enable latch bit, it is only valid for the write status register command to change the volatile status register bit values. figure 4a. write enable for volatile status register sequence diagram (qpi) cs # sclk io 0 io 1 io 2 io 3 0 1 command 50 h
18 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash figure 5. read status register sequence diagram command 0 1 2 3 4 5 6 7 05 h or 35 h cs # sclk si so high -z 8 9 10 11 12 13 14 15 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 msb s7~s 0 or s 15 ~s 8 out s7~s 0 or s 15 ~s 8 out msb 7.4. read status register (rdsr) (05h or 35h) the read status register (rdsr) command is for reading the status register. the status register may be read at any time, even while a program, erase or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new command to the device. it is also possible to read the status register continuously. for command code 05h, the so will output status register bits s7~s0. the command code 35h, the so will output status register bits s15~s8. figure 5a. read status register sequence diagram (qpi) cs # sclk io 0 io 1 io 2 io 3 0 1 2 3 4 5 command 05 h or 35 h 4 4 0 0 5 5 1 1 4 5 6 2 6 2 6 7 3 7 3 7 s 7 - s 0 or s 15 - s 8 out
19 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash figure 6. write status register sequence diagram command 0 1 2 3 4 5 6 7 01h cs# sclk si so high-z 8 9 10 11 12 13 14 15 msb 7 6 5 4 3 2 1 0 status register in 16 17 18 19 20 21 22 23 15 14 13 12 11 10 9 8 7.5. write status register (wrsr) (01h) the write status register (wrsr) command allows new values to be written to the status register. before it can be accepted, a write enable (wren) command must previously have been executed. after the write enable (wren) command has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) command has no effect on s15, s10, s1 and s0 of the status register. cs# must be driven high after the eighth or sixteen bit of the data byte has been latched in. if not, the write status register (wrsr) command is not executed. if cs# is driven high after eighth bit of the data byte, the cmp and qe and srp1 bits will be cleared to 0. as soon as cs# is driven high, the self-timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) is reset. the write status register (wrsr) command allows the user to change the values of the block protect (bp4, bp3, bp2, bp1 and bp0) bits, to define the size of the area that is to be treated as read-only, as defined in ta - ble1. the write status register (wrsr) command also allows the user to set or reset the status register protect (srp1 and srp0) bits in accordance with the write protect (wp#) signal. the status register protect (srp1 and srp0) bits and write protect (wp#) signal allow the device to be put in the hardware protected mode. the write status register (wrsr) command is not executed once the hardware protected mode is entered. figure 6a. write status register sequence diagram (qpi) c s # s c l k i o 0 i o 1 i o 2 i o 3 0 1 2 3 4 5 c o m m a n d 0 1 h 4 1 2 0 8 5 1 3 1 9 1 4 1 0 7 3 1 5 1 1 s t a t u s r e g i s t e r i n 6 2
20 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7.6. read data bytes (read) (03h) the read data bytes (read) command is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of sclk. then the memory content, at that address, is shifted out on so, each bit being shifted out, at a max frequency f r , during the falling edge of sclk. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes (read) command. any read data bytes (read) command, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 7. read data bytes sequence diagram command 0 1 2 3 4 5 6 7 03 h cs # sclk si so high -z 8 9 10 28 29 30 31 32 msb 3 2 1 0 34 35 36 37 33 23 22 21 7 6 5 4 3 2 1 0 38 39 24 - bit address msb data out 1 data out 2 7.7. read data bytes at higher speed (fast read) (0bh) the read data bytes at higher speed (fast read) command is for quickly reading data out. it is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of sclk. then the memory content, at that address, is shifted out on so, each bit being shifted out, at a max frequency f c , during the falling edge of sclk. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. figure 8. read data bytes at higher speed sequence diagram
21 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash fast read (0bh) in qpi mode the fast read command is also supported in qpi mode. in qpi mode, the number of dummy clocks is configured by the set read parameters (c0h) command to accommodate a wide range application with different needs for either maximum fast read frequency or minimum data access latency. depending on the read parameter bits p[5:4] setting, the number of dummy clocks can be configured as either 4/6/8. figure 8a. read data bytes at higher speed sequence diagram (qpi) cs # sclk io 0 io 1 io 2 io 3 0 1 2 3 4 5 command 0 bh 20 12 16 8 6 7 8 9 10 4 4 0 0 4 0 4 0 4 21 13 17 9 5 5 1 1 5 1 5 1 5 22 14 18 10 6 6 2 2 6 2 6 2 6 23 15 19 11 7 7 3 3 7 3 7 3 7 a 23 - 16 a 15 - 8 a 7 - 0 dummy * 11 12 13 ios switch from input to output byte 1 byte 2 *" set read parameters " command ( c 0 h ) can set the number of dummy clocks 7. 8 . dual output fast read (3bh) the dual output fast read command is followed by 3-byte address (a23-a0) and a dummy byte, each bit being latched in during the rising edge of sclk, then the memory contents are shifted out 2-bit per clock cycle from si and so. the command sequence is shown in followed figure9. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. figure 9. dual output fast read sequence diagram
22 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7. 9 . quad output fast read (6bh) the quad output fast read command is followed by 3-byte address (a23-a0) and a dummy byte, each bit being latched in during the rising edge of sclk, then the memory contents are shifted out 4-bit per clock cycle from io3, io2, io1 and io0. the command sequence is shown in followed figure10. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. figure 10. quad output fast read sequence diagram command 0 1 2 3 4 5 6 7 6bh cs # sclk si( io 0) so( io 1) high -z 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24 - bit address 34 35 36 37 33 1 5 1 5 1 5 1 38 39 byte1 32 42 43 44 45 41 46 47 40 5 dummy clocks 0 4 0 4 0 4 0 4 4 5 wp #( io 2) high -z hold #( io 3) high -z cs # sclk si( io 0) so( io 1) wp #( io 2) hold #( io 3) 2 6 2 6 2 6 2 6 6 3 7 3 7 3 7 3 7 7 byte2 byte3 byte4 7. 1 0 . dual i/o fast read (bbh) the dual i/o fast read command is similar to the dual output fast read command but with the capability to input the 3-byte address (a23-0) and a continuous read mode byte 2-bit per clock by si and so, each bit being latched in during the rising edge of sclk, then the memory contents are shifted out 2-bit per clock cycle from si and so. the command sequence is shown in followed figure11. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. dual i/o fast read with continuous read mode the dual i/o fast read command can further reduce command overhead through setting the continuous read mode bits (m7-0) after the input 3-byte address (a23-a0). if the continuous read mode bits (m5-4) =(1, 0), then the next dual i/o fast read command (after cs# is raised and then lowered) does not require the bbh command code. the command sequence is shown in followed figure11. if the continuous read mode bits (m5-4) do not equal (1, 0), the next command requires the first bbh command code, thus returning to normal operation. a continuous read mode reset command can be used to reset (m5-4) before issuing normal command.
23 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash figure 11. dual i/o fast read sequence diagram (m5-4 (1, 0)) command 0 1 2 3 4 5 6 7 bbh cs # sclk si( io 0) so( io 1) 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 16 17 18 19 20 21 22 23 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 a 23 - 16 a 15 -8 a7-0 m7-0 cs # 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 si( io 0) so( io 1) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 sclk 6 7 byte1 byte2 byte3 byte4 figure 11a. dual i/o fast read sequence diagram (m5-4 = (1, 0 )) 0 1 2 3 4 5 6 7 cs # sclk 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 a 23 - 16 a 15 -8 a7-0 m7-0 cs # 23 24 25 26 27 28 29 30 31 si( io 0) so( io 1) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 sclk 6 7 byte1 byte2 byte3 byte4 15 16 17 18 19 20 21 22 7. 1 1 . quad i/o fast read (ebh) the quad i/o fast read command is similar to the dual i/o fast read command but with the capability to input the 3-byte address (a23-0) and a continuous read mode byte and 4-dummy clock 4-bit per clock by io0, io1, io3, io4, each bit being latched in during the rising edge of sclk, then the memory contents are shifted out 4-bit per clock cycle from io0, io1, io2, io3. the command sequence is shown in followed figure12. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the quad enable bit (qe) of status register (s9) must be set to enable for the quad i/o fast read command.
24 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash quad i/o fast read with continuous read mode the quad i/o fast read command can further reduce command overhead through setting the continuous read mode bits (m7-0) after the input 3-byte address (a23-a0). if the continuous read mode bits (m5-4) = (1, 0), then the next quad i/o fast read command (after cs# is raised and then lowered) does not require the ebh command code. the command sequence is shown in followed figure12a. if the continuous read mode bits (m5-4) do not equal to (1, 0), the next command requires the first ebh command code, thus returning to normal operation. a continuous read mode reset command can be used to reset (m5-4) before issuing normal command. figure 12. quad i/o fast read sequence diagram (m5-4 (1, 0)) command 0 1 2 3 4 5 6 7 ebh cs # sclk si( io 0) so( io 1) 8 9 10 11 12 13 14 15 4 0 4 0 4 0 4 0 16 17 18 19 20 21 22 23 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 a 23 - 16 a 15 -8 a7-0 m7-0 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 wp #( io 2) hold #( io 3) 4 5 6 7 dummy byte1 byte2 figure 12a. quad i/o fast read sequence diagram (m5-4 = (1, 0)) 0 1 2 3 4 5 6 7 cs # sclk 8 9 10 11 12 13 14 15 si( io 0) so( io 1) wp #( io 2) hold #( io 3) 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 5 6 7 a 23 - 16 a 15 -8 a7-0 m7-0 dummy byte1 byte2 quad i/o fast read with 8/16/32/64-byte wrap around in standard spi mode the quad i/o fast read command can be used to access a specific portion within a page by issuing set burst with wrap (77h) commands prior to ebh. the set burst with wrap (77h) command can either enable or disable the wrap around feature for the following ebh commands. when wrap around is enabled, the data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. the output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary automatically until cs# is pulled high to terminate the command.
25 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash the burst with wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. the set burst with wrap command allows three wrap bits w6-w4 to be set. the w4 bit is used to enable or disable the wrap around operation while w6-w5 is used to specify the length of the wrap around section within a page. quad i/o fast read (ebh) in qpi mode the quad i/o fast read command is also supported in qpi mode. see figure12b. in qpi mode, the number of dummy clocks is configured by the set read parameters (c0h) command to accommodate a wide range application with different needs for either maximum fast read frequency or minimum data access latency. depending on the read parameter bits p[5:4] setting, the number of dummy clocks can be configured as either 4/6/8. in qpi mode, the continuous read mode bits m7-m0 are also considered as dummy clocks. continuous read mode feature is also available in qpi mode for quad i/o fast read command. wrap around feature is not available in qpi mode for quad i/o fast read command. to perform a read operation with fixed data length wrap around in qpi mode, a dedicated burst read with wrap (0ch) command must be used. figure 12b. quad i/o fast read sequence diagram (m5-4 = (1, 0) qpi) c s # s c l k i o 0 i o 1 i o 2 i o 3 0 1 2 3 4 5 c o m m a n d e b h 2 0 1 2 1 6 8 6 7 8 9 1 0 4 4 0 0 4 0 4 0 4 2 1 1 3 1 7 9 5 5 1 1 5 1 5 1 5 2 2 1 4 1 8 1 0 6 6 2 2 6 2 6 2 6 2 3 1 5 1 9 1 1 7 7 3 3 7 3 7 3 7 a 2 3 - 1 6 a 1 5 - 8 a 7 - 0 m 7 - 0 * 1 1 1 2 1 3 1 4 i o s s w i t c h f r o m i n p u t t o o u t p u t b y t e 1 b y t e 2 b y t e 3 * " s e t r e a d p a r a m e t e r s " c o m m a n d ( c 0 h ) c a n s e t t h e n u m b e r o f d u m m y c l o c k s 7. 1 2 . quad i/o word fast read (e7h) the quad i/o word fast read command is similar to the quad i/o fast read command except that the lowest address bit (a0) must equal 0 and only 2-dummy clock. the command sequence is shown in followed figure13. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the quad enable bit (qe) of status register (s9) must be set to enable for the quad i/o word fast read command. quad i/o word fast read with continuous read mode the quad i/o word fast read command can further reduce command overhead through setting the continuous read mode bits (m7-0) after the input 3-byte address (a23-a0). if the continuous read mode bits (m5-4) = (1, 0), then the next quad i/o word fast read command (after cs# is raised and then lowered) does not require the e7h command code. the command sequence is shown in followed figure13. if the continuous read mode bits (m5-4) do not equal to (1, 0), the next command requires the first e7h command code, thus returning to
26 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash figure 13a. quad i/o word fast read sequence diagram (m5-4 = (1, 0)) 0 1 2 3 4 5 6 7 cs # sclk 8 9 10 11 12 13 14 15 si( io 0) so( io 1) wp #( io 2) hold #( io 3) 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 4 5 6 7 a 23 - 16 a 15 -8 a7-0 m7-0 dummy byte1 byte2 4 0 5 1 6 2 7 3 byte3 normal operation. a continuous read mode reset command can be used to reset (m5-4) before issuing normal command. figure 13. quad i/o word fast read sequence diagram (m5-4 (1, 0) ) command 0 1 2 3 4 5 6 7 e7h cs # sclk si( io 0) so( io 1) 8 9 10 11 12 13 14 15 4 0 4 0 4 0 4 0 16 17 18 19 20 21 22 23 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 a 23 - 16 a 15 -8 a7-0 m7-0 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 wp #( io 2) hold #( io 3) 4 5 6 7 dummy byte1 byte2 4 0 5 1 6 2 7 3 byte3 quad i/o word fast read with 8/16/32/64-byte wrap around in standard spi mode the quad i/o word fast read command can be used to access a specific portion within a page by issuing set burst with wrap (77h) commands prior to e7h. the set burst with wrap (77h) command can either enable or disable the wrap around feature for the following e7h commands. when wrap around is enabled, the data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. the output data starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning boundary automatically until cs# is pulled high to terminate the command. the burst with wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. the set burst with wrap command allows three wrap bits w6-w4 to be set. the w4 bit is used to enable or disable the wrap around operation while w6-w5 is used to specify the length of the wrap around section within a page.
27 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash w6, w5 w4=0 w4=1 (default) wrap around wrap length wrap around wrap length 0, 0 yes 8-byte no n/a 0, 1 yes 16 -byte no n/a 1, 0 yes 32 -byte no n/a 1, 1 yes 64 -byte no n/a if the w6-w4 bits are set by the set burst with wrap command, all the following quad i/o fast read and quad i/o word fast read command will use the w6-w4 setting to access the 8/16/32/64-byte section within any page. to exit the wrap around function and return to normal read operation, another set burst with wrap command should be issued to set w4=1. in qpi mode, the burst read with wrap (0ch) command should be used to perform the read operation with wrap around feature. the wrap length set by w5-w6 in standard spi mode is still valid in qpi mode and can also be re-configured by set read parameters (c0h) command. 7. 1 3 . set burst with wrap (77h) the set burst with wrap command is used in conjunction with quad i/o fast read and quad i/o word fast read command to access a fixed length of 8/16/32/64-byte section within a 256-byte page, in standard spi mode. the set burst with wrap command sequence: cs# goes low send set burst with wrap command send 24 dummy bits send 8 bits wrap bits cs# goes high. figure 14. set burst with wrap sequence diagram command 0 1 2 3 4 5 6 7 77 h cs # sclk si ( io 0 ) so ( io 1 ) 8 9 10 11 12 13 14 15 x x x x x x 4 x x x x x x x 5 x w 6 - w 4 x x x x x x 6 x x x x x x x x x wp # ( io 2 ) hold # ( io 3 ) 7. 14 . page program (pp) (02h) the page program (pp) command is for programming the memory. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit before sending the page program command. the page program (pp) command is entered by driving cs# low, followed by the command code, three address bytes and at least one data byte on si. if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7-a0) are all zero). cs# must be driven low for the entire duration of the sequence. the page program command sequence: cs# goes low sending page program
28 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash figure 15. page program sequence diagram figure 15a. page program sequence diagram (qpi) cs # sclk io 0 io 1 io 2 io 3 0 1 2 3 4 5 command 02 h 20 12 16 8 6 7 8 9 10 4 4 0 0 4 0 4 0 21 13 17 9 5 5 1 1 5 1 5 1 22 14 18 10 6 6 2 2 6 2 6 2 23 15 19 11 7 7 3 3 7 3 7 3 a 23 - 16 a 15 - 8 a 7 - 0 11 12 13 byte 1 byte 2 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 5 1 6 5 1 7 5 1 8 5 1 9 byte 3 byte 255 byte 256 command 3-byte address on si at least 1 byte data on si cs# goes high. the command sequence is shown in figure15. if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. cs# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the page program (pp) command is not executed. as soon as cs# is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a page program (pp) command applied to a page which is protected by the block protect (bp4, bp3, bp2, bp1 and bp0) is not executed.
29 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7. 15 . quad page program (32h) the quad page program command is for programming the memory using four pins: io0, io1, io2 and io3. to use quad page program the quad enable in status register bit9 must be set (qe = 1). a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit before sending the page program command. the quad page program command is entered by driving cs# iow, followed by the command code (32h), three address bytes and at least one data byte on io pins. the command sequence is shown in figure 16. if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. cs# must be driven high after the eighth bit of the last data byte has been latched in, otherwise the quad page program (pp) command is not e xecuted. as soon as cs# is driven high, the self-timed quad page program cycle (whose duration is t pp ) is initiated. while the quad page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed quad page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a quad page program command applied to a page which is protected by the block protect (bp4, bp3, bp2, bp1 and bp0) is not executed. figure 16. quad page program sequence diagram c o m m a n d 0 1 2 3 4 5 6 7 3 2 h c s # s c l k 8 9 1 0 2 8 2 9 3 0 3 1 3 2 1 0 2 3 2 2 2 1 2 4 - b i t a d d r e s s 3 2 3 3 3 4 3 5 4 0 m s b 3 6 3 7 3 8 3 9 s i ( i o 0 ) s o ( i o 1 ) w p # ( i o 2 ) h o l d # ( i o 3 ) 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 b y t e 1 b y t e 2 c s # s c l k s i ( i o 0 ) s o ( i o 1 ) w p # ( i o 2 ) h o l d # ( i o 3 ) 4 2 4 3 4 4 4 5 4 1 4 6 4 7 4 0 5 0 5 1 5 2 5 3 4 9 5 4 5 5 4 8 5 3 6 5 3 7 5 3 8 5 3 9 5 4 0 5 4 1 5 4 2 5 4 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 b y t e 1 1 4 0 5 1 6 2 7 3 b y t e 1 2 4 0 5 1 6 2 7 3 b y t e 2 5 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 b y t e 2 5 6
30 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7. 16 . sector erase (se) (20h) the sector erase (se) command is for erasing the all data of the chosen sector. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit. the sector erase (se) command is entered by driving cs# low, followed by the command code, and 3- byte address on si. any address inside the sector is a valid address for the sector erase (se) command. cs# must be driven low for the entire duration of the sequence. the sector erase command sequence: cs# goes low sending sector erase command 3-byte address on si cs# goes high. the command sequence is shown in figure17. cs# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the sector erase (se) command is not executed. as soon as cs# is driven high, the self-timed sector erase cycle (whose duration is t se ) is initiated. while the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a sector erase (se) command applied to a sector which is protected by the block protect (bp4, bp3, bp2, bp1 and bp0) bit (see table1 & table1a) is not executed. figure 17. sector erase sequence diagram command 0 1 2 3 4 5 6 7 20 h cs# s cl k si 8 9 29 30 31 msb 2 1 0 24 bits address 23 22 figure 17a. sector erase sequence diagram (qpi) c s # s c l k i o 0 i o 1 i o 2 i o 3 0 1 2 3 4 5 c o m m a n d 2 0 h 2 0 1 2 1 6 8 a 2 3 - 1 6 a 1 2 - 8 6 7 0 2 1 1 3 1 7 9 1 2 3 1 5 1 9 1 1 3 2 2 1 4 1 8 1 0 2 4 5 6 7 a 7 - 0
31 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7. 17 . 32kb block erase (be) (52h) the 32kb block erase (be) command is for erasing the all data of the chosen block. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit. the 32kb block erase (be) command is entered by driving cs# low, followed by the command code, and three address bytes on si. any address inside the block is a valid address for the 32kb block erase (be) command. cs# must be driven low for the entire duration of the sequence. the 32kb block erase command sequence: cs# goes low sending 32kb block erase command 3-byte address on si cs# goes high. the command sequence is shown in figure18. cs# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 32kb block erase (be) command is not executed. as soon as cs# is driven high, the self-timed block erase cycle (whose duration is t be ) is initiated. while the block erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed block erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a 32kb block erase (be) command applied to a block which is protected by the block protect (bp4, bp3, bp2, bp1 and bp0) bits (see table1 & table1a) is not executed. figure 18. 32kb block erase sequence diagram command 0 1 2 3 4 5 6 7 52 h cs# s cl k si 8 9 29 30 31 msb 2 1 0 24 bits address 23 22 figure 18a. 32kb block erase sequence diagram (qpi) c s # s c l k i o 0 i o 1 i o 2 i o 3 0 1 2 3 4 5 c o m m a n d 5 2 h 2 0 1 2 1 6 8 a 2 3 - 1 6 a 1 2 - 8 6 7 0 2 1 1 3 1 7 9 1 2 3 1 5 1 9 1 1 3 2 2 1 4 1 8 1 0 2 4 5 6 7 a 7 - 0
32 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7. 18 . 64kb block erase (be) (d8h) the 64kb block erase (be) command is for erasing the all data of the chosen block. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit. the 64kb block erase (be) command is entered by driving cs# low, followed by the command code, and three address bytes on si. any address inside the block is a valid address for the 64kb block erase (be) command. cs# must be driven low for the entire duration of the sequence. the 64kb block erase command sequence: cs# goes low sending 64kb block erase command 3-byte address on si cs# goes high. the command sequence is shown in figure19. cs# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64kb block erase (be) command is not executed. as soon as cs# is driven high, the self-timed block erase cycle (whose duration is t be ) is initiated. while the block erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed block erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a 64kb block erase (be) command applied to a block which is protected by the block protect (bp4, bp3, bp2, bp1 and bp0) bits (see table1 & table1a ) is not executed. figure 19. 64kb block erase sequence diagram command 0 1 2 3 4 5 6 7 d8h cs # sc lk si 8 9 29 30 31 msb 2 1 0 24 bits address 23 22 figure 19a. 64 kb block erase sequence diagram (qpi) c s # s c l k i o 0 i o 1 i o 2 i o 3 0 1 2 3 4 5 c o m m a n d d 8 h 6 7 a 2 3 - 1 6 a 1 5 - 8 a 7 - 0 2 0 1 6 1 2 8 4 0 1 3 9 5 1 1 4 1 0 6 2 1 5 1 1 7 3 2 3 1 9 2 2 1 8 2 1 1 7
33 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7. 19 . chip erase (ce) (60/c7h) the chip erase (ce) command is for erasing the all data of the chip. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit. the chip erase (ce) command is entered by driving cs# low, followed by the command code on serial data input (si). cs# must be driven low for the entire duration of the sequence. the chip erase command sequence: cs# goes low sending chip erase command cs# goes high. the command sequence is shown in figure20. cs# must be driven high after the eighth bit of the command code has been latched in, otherwise the chip erase command is not executed. as soon as cs# is driven high, the self- timed chip erase cycle (whose duration is t ce ) is initiated. while the chip erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed chip erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the chip erase (ce) command is executed only if all block protect (bp4,bp3,bp2, bp1 and bp0) bits are set to none protected. the chip erase (ce) command is ignored if one or more sectors are protected. figure 20. chip erase sequence diagram command 0 1 2 3 4 5 6 7 60h or c7h cs# sc lk si figure 20a. chip erase sequence diagram (qpi) cs # sclk io 0 io 1 io 2 io 3 0 1 instruction c 7 h / 60 h
34 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7. 2 0 . deep power-down (dp) (b9h) executing the deep power-down (dp) command is the only way to put the device in the lowest consumption mode (the deep power-down mode). it can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all write, program and erase commands. driving cs# high deselects the device, and puts the device in the standby mode (if there is no internal cycle currently in progress). but this mode is not the deep power-down mode. the deep power-down mode can only be entered by executing the deep power-down (dp) command. once the device has entered the deep power-down mode, all commands are ignored except the release from deep power-down and read device id (rdi) command. this releases the device from this mode. the release from deep power-down and read device id (rdi) command also allows the device id of the device to be output on so. the deep power-down mode automatically stops at power-down, and the device always power-up in the standby mode. the deep power-down (dp) command is entered by driving cs# low, followed by the command code on si. cs# must be driven low for the entire duration of the sequence. the deep power-down command sequence: cs# goes low sending deep power-down command cs# goes high. the command sequence is shown in figure21. cs# must be driven high after the eighth bit of the command code has been latched in; otherwise the deep power-down (dp) command is not executed. as soon as cs# is driven high, it requires a delay of t dp before the supply current is reduced to i cc2 and the deep power- down mode is entered. any deep power-down (dp) command, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 21. deep power-down sequence diagram command 0 1 2 3 4 5 6 7 b9 h c s # s c lk si t dp stand-by mode deep power-down mode figure 21a. deep power-down sequence diagram (qpi) c s # s c l k i o 0 i o 1 i o 2 i o 3 0 1 c o m m a n d b 9 h t d p d e e p p o w e r - d o w n m o d e s t a n d - b y m o d e
35 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7. 2 1 . release from deep power-down and read device id (rdi) (abh) the release from power-down and read device id is a multi-purpose command. it can be used to release the device from the power-down state or obtain the devices electronic identification (id) number. to release the device from the power-down state, the command is issued by driving the cs# pin low, shifting the instruction code abh and driving cs# high as shown in figure22. release from power-down will take the time duration of t res1 (see ac characteristics) before the device will resume normal operation and other command are accepted. the cs# pin must remain high during the t res1 time duration. when used only to obtain the device id while not in the power-down state, the command is initiated by driving the cs# pin low and shifting the instruction code abh followed by 3-dummy byte. the device id bits are then shifted out on the falling edge of sclk with most significant bit (msb) first as shown in figure23. the device id value for the GD25LQ40 is listed in manufacturer and device identification table. the device id can be read continuously. the command is completed by driving cs# high. when used to release the device from the power-down state and obtain the device id, the command is the same as previously described, and shown in figure2 3 , except that after cs# is driven high it must remain high for a time duration of t res2 (see ac characteristics). after this time duration the device will resume normal operation and other command will be accepted. if the release from power-down/device id command is issued while an erase, program or write cycle is in process (when wip equal 1) the command is ignored and will not have any effects on the current cycle. figure 22. release power-down sequence diagram command 0 1 2 3 4 5 6 7 abh cs # sclk si res 1 stand - by mode deep power - down mode t figure 22a. release power-down sequence diagram (qpi) cs # sclk io 0 io 1 io 2 io 3 0 1 command abh tres 1 deep power - down mode stand - by mode
36 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash figure 23. release power-down and read device id sequence diagram figure 23a. release power-down and read device id sequence diagram (qpi) cs # sclk io 0 io 1 io 2 io 3 0 1 2 3 4 5 command abh 6 7 8 0 1 3 4 5 7 2 6 ios switch from input to output 3 dummy bytes device id tres 2 deep power - down mode stand - by mode
37 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7. 2 2 . read manufacture id/device id (rems) (90h) the read manufacturer/device id command is an alternative to the release from power-down/device id command that provides both the jedec assigned manufacturer id and the specific device id. the command is initiated by driving the cs# pin low and shifting the command code 90h followed by a 24-bit address (a23-a0) of 000000h. after which, the manufacturer id and the device id are shifted out on the falling edge of sclk with most significant bit (msb) first as shown in figure24. if the 24-bit address is initially set to 000001h, the device id will be read first. figure 24. read manufacture id/device id sequence diagram figure 24a. read manufacture id/device id sequence diagram (qpi) c s # s c l k i o 0 i o 1 i o 2 i o 3 0 1 2 3 4 5 c o m m a n d 9 0 h 6 7 8 0 1 3 4 5 7 2 6 i o s s w i t c h f r o m i n p u t t o o u t p u t d e v i c e i d m i d 0 4 1 5 2 6 3 7 3 7 2 6 1 5 0 4 9 1 0 a 2 3 - 1 6 a 1 5 - 8 a 7 - 0 8 9 1 9 1 2 1 3 2 3 1 0 1 4 1 1 1 5 1 8 2 2 1 7 2 1 1 6 2 0 ( 0 0 h )
38 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7. 2 3 . read manufacture id/device id dual i/o (92h) the read manufacturer/device id dual i/o command is an alternative to the release from power-down/ device id command that provides both the jedec assigned manufacturer id and the specific device id by dual i/o. the command is initiated by driving the cs# pin low and shifting the command code 92h followed by a 24-bit address (a23-a0) of 000000h. after which, the manufacturer id and the device id are shifted out on the falling edge of sclk with most significant bit (msb) first as shown in figure25. if the 24-bit address is initially set to 000001h, the device id will be read first. figure 25. read manufacture id/device id dual i/o sequence diagram command 0 1 2 3 4 5 6 7 92h cs# sclk si(io0) so(io1) 8 9 10 11 12 13 14 15 6 4 2 0 6 4 2 0 16 17 18 19 20 21 22 23 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 a23-16 a15-8 a7-0 m7-0 cs# 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 si(io0) so(io1) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 sclk mfr id device id 40 41 42 43 6 4 2 0 7 5 3 1 44 45 46 47 6 4 2 0 7 5 3 1 mfr id (repeat) device id (repeat) mfr id (repeat) device id (repeat)
39 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash figure 26. read manufacture id/device id quad i/o sequence diagram c o m m a n d 0 1 2 3 4 5 6 7 9 4 h c s # s c l k s i ( i o 0 ) s o ( i o 1 ) 8 9 1 0 1 1 1 2 1 3 1 4 1 5 4 0 4 0 4 0 4 0 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 a 2 3 - 1 6 a 1 5 - 8 a 7 - 0 m 7 - 0 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 w p # ( i o 2 ) h o l d # ( i o 3 ) d u m m y m f r i d d i d c s # s c l k s i ( i o 0 ) s o ( i o 1 ) w p # ( i o 2 ) h o l d # ( i o 3 ) 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 m f r i d ( r e p e a t ) d i d ( r e p e a t ) 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 m f r i d ( r e p e a t ) d i d ( r e p e a t ) 7. 24 . read manufacture id/device id quad i/o (94h) the read manufacturer/device id quad i/o command is an alternative to the release from power-down/ device id command that provides both the jedec assigned manufacturer id and the specific device id by quad i/o. the command is initiated by driving the cs# pin low and shifting the command code 94h followed by a 24-bit address (a23-a0) of 000000h. after which, the manufacturer id and the device id are shifted out on the falling edge of sclk with most significant bit (msb) first as shown in figure26. if the 24-bit address is initially set to 000001h, the device id will be read first.
40 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7. 25 . read identification (rdid) (9fh) the read identification (rdid) command allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. the device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. the read identification (rdid) command while an erase or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the read identification (rdid) command should not be issued while the device is in deep power-down mode. the device is first selected by driving cs# to low. then, the 8-bit command code for the command is shifted in. this is followed by the 24-bit device identification, stored in the memory, being shifted out on serial data output, each bit being shifted out during the falling edge of serial clock. the command sequence is shown in figure27. the read identification (rdid) command is terminated by driving cs# to high at any time during data output. when cs# is driven high, the device is put in the standby mode. once in the standby mode, the device waits to be selected, so that it can receive, decode and execute commands. figure 27. read identification id sequence diagram 0 1 2 3 4 5 6 7 cs # sclk si so 8 9 10 msb 18 19 20 21 17 6 5 4 3 2 1 0 22 23 16 26 27 28 29 25 30 31 24 7 capacity id 7- id 0 cs # sclk si so msb memory type id 15 - id 8 6 5 4 3 2 1 0 7 11 12 13 14 15 9 fh 6 5 4 3 2 1 0 7 manufacturer id msb figure 27a. read identification id sequence diagram (qpi) c s # s c l k i o 0 i o 1 i o 2 i o 3 0 1 2 3 4 5 c o m m a n d 9 f h 1 2 8 6 0 1 3 9 1 1 5 1 1 3 1 4 1 0 2 4 5 6 7 i o s s w i t c h f r o m i n p u t t o o u t p u t m i d i d 1 5 - 8 i d 7 - 0 0 1 3 2 4 5 6 7
41 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7. 26 . program/erase suspend (pes) (75h) the program/erase suspend command 75h, allows the system to interrupt a page program or sector/block erase operation and then read data from any other sector or block. the write status register command (01h) and erase security registers (44h, 42h) and erase commands (20h, 52h, d8h, c7h, 60h) and page program command are not allowed during program/erase suspend. program/erase suspend is valid only during the page program or sector/block erase operation. a maximum of time of tsus (see ac characteristics) is required to suspend the program/erase operation. the program/erase suspend command will be accepted by the device only if the sus2/sus1 bit in the status register equal to 0 and wip bit equal to 1 while a page program or a sector or block erase operation is on- going. if the sus2/sus1 bit equal to 1 or wip bit equal to 0, the suspend command will be ignored by the device. the wip bit will be cleared form 1 to 0 within tsus and the sus2/sus1 bit will be set from 0 to 1 immediately after program/erase suspend. a power-off during the suspend period will reset the device and release the suspend state. the command sequence is show in figure28. figure 28. program/erase suspend sequence diagram command 0 1 2 3 4 5 6 7 75 h cs # sclk si so high -z tsus accept read command figure 28a. program/erase suspend sequence diagram (qpi) cs # sclk io 0 io 1 io 2 io 3 0 1 command 75 h tsus accept read
42 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7. 27 . program/erase resume (per) (7ah) the program/erase resume command must be written to resume the program or sector/block erase operation after a program/erase suspend command. the program/erase command will be accepted by the device only if the sus2/sus1 bit equal to 1 and the wip bit equal to 0. after issued the sus2/sus1 bit in the status register will be cleared from 1 to 0 immediately, the wip bit will be set from 0 to 1 within 200ns and the sector or block will complete the erase operation or the page will complete the program operation. the program/erase resume command will be ignored unless a program/erase suspend is active. the command sequence is show in figure29. figure 29. program/erase resume sequence diagram command 0 1 2 3 4 5 6 7 7ah cs# sclk si so resume erase/program figure 29a. program/erase resume sequence diagram (qpi) cs # sclk io 0 io 1 io 2 io 3 0 1 command 7 ah resume previously suspended program or erase
43 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7. 28 . erase security registers (44h) the GD25LQ40 provides three 256-byte security registers which c an be erased and programmed individually. these registers may be used by the system manufacturers to store security and other important information separately from the main memory array. the erase security registers command is similar to sector/block erase command. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit. the erase security registers command sequence: cs# goes low sending erase security registers command cs# goes high. the command sequence is shown in figure30. cs# must be driven high after the eighth bit of the command code has been latched in; otherwise the erase security registers command is not executed. as soon as cs# is driven high, the self-timed erase security registers cycle (whose duration is t se ) is initiated. while the erase security registers cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed erase security registers cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the security registers lock bit (lb3-1) in the status register can be used to otp protect the security registers. once the lb bit is set to 1, the security registers will be permanently locked; the erase security registers command will be ignored. address a23-16 a15-12 a11-8 a7-0 security register #1 00h 0 0 0 1 0 0 0 0 do not care security register #2 00h 0 0 1 0 0 0 0 0 do not care security register #3 00h 0 0 1 1 0 0 0 0 do not care figure 30. erase security registers command sequence diagram command 0 1 2 3 4 5 6 7 44 h cs # sclk si 8 9 29 30 31 msb 2 1 0 24 bits address 23 22
44 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7. 29 . program security registers (42h) the program security registers command is similar to the page program command. it allows from 1 to 256 bytes security registers data to be programmed. a write enable (wren) command must previously have been executed to set the write enable latch (wel) bit before sending the program security registers command. the program security registers command is entered by driving cs# low, followed by the command code (42h), three address bytes and at least one data byte on si. as soon as cs# is driven high, the self-timed program security registers cycle (whose duration is t pp ) is initiated. while the program security registers cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed program security registers cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. if the security registers lock bit (lb3-1) is set to 1, the security registers will be permanently locked. program security registers command will be ignored. address a23-16 a15-12 a11-8 a7-0 security register #1 00h 0 0 0 1 0 0 0 0 byte address security register #2 00h 0 0 1 0 0 0 0 0 byte address security register #3 00h 0 0 1 1 0 0 0 0 byte address figure 31. program security registers command sequence diagram command 0 1 2 3 4 5 6 7 42 h cs # sclk si 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24 - bit address 42 43 44 45 41 46 47 40 50 51 52 53 49 54 55 48 6 5 4 3 2 1 0 7 cs # sclk si msb data byte 2 32 33 34 35 7 6 5 4 3 2 1 0 msb 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 data byte 1 data byte 3 data byte 256 msb msb msb 36 37 38 39 2072 2073 2074 2075 2076 2077 2078 2079
45 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash address a23-16 a15-12 a11-8 a7-0 security register #0 00h 0 0 0 0 0 0 0 0 byte address security register #1 00h 0 0 0 1 0 0 0 0 byte address security register #2 00h 0 0 1 0 0 0 0 0 byte address security register #3 00h 0 0 1 1 0 0 0 0 byte address figure 32. read security registers command sequence diagram command 0 1 2 3 4 5 6 7 48 h cs # sclk si so high -z 8 9 10 28 29 30 31 3 2 1 0 23 22 21 24 - bit address msb 34 35 36 37 33 6 5 4 3 2 1 0 38 39 data out 1 32 42 43 44 45 41 46 47 40 7 6 5 4 3 2 1 0 7 6 5 7 data out 2 cs # sclk si so msb dummy byte 7. 3 0 . read security registers (48h) the read security registers command is similar to fast read command. the command is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of sclk. then the memory content, at that address, is shifted out on so, each bit being shifted out, at a max frequency f c , during the falling edge of sclk. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. once the a9-a0 address reaches the last byte of the register (byte 3ffh), it will reset to 000h, the command is completed by driving cs# high.
46 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7. 3 1 . set read parameters (c0h) in qpi mode the set read parameters (c0h) command can be used to configure the number of dummy clocks for fast read (0bh), quad i/o fast read (ebh) and burst read with wrap (0ch) command, and to configure the number of bytes of wrap length for the burst read with wrap (0ch) command. the wrap length is set by w5-6 bit in the set burst with wrap (77h) command. this setting will remain unchanged when the device is switched from standard spi mode to qpi mode. p5-p4 dummy clocks maximum read freq. p 1-p0 wrap length 0 0 4 8 0mhz 0 0 8-byte 0 1 4 80mhz 0 1 16 -byte 1 0 6 12 0mhz 1 0 32 -byte 1 1 8 12 0mhz 1 1 64 -byte figure 33. set read parameters command sequence diagram cs # sclk io 0 io 1 io 2 io 3 0 1 2 3 command c 0 h p 4 p 0 p 6 p 2 p 7 p 3 p 5 p 1 read parameters
47 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7. 3 2 . burst read with wrap (0ch) t he burst read with wrap (0ch) command provides an alternative way to perform the read operation with wrap around in qpi mode. this command is similar to the fast read (0bh) command in qpi mode , except the addressing of the read operation will wrap around to the beginning boundary of the wrap around once the ending boundary is reached. the w rap length and the number of dummy clocks can be configured by the set read param eters (c0h) command. figure 34. burst read with wrap command sequence diagram cs # sclk io 0 io 1 io 2 io 3 0 1 2 3 4 5 command 0 ch 20 12 16 8 6 7 8 9 10 4 0 4 0 4 0 4 21 13 17 9 5 1 5 1 5 1 5 22 14 18 10 6 2 6 2 6 2 6 23 15 19 11 7 3 7 3 7 3 7 a 23 - 16 a 15 - 8 a 7 - 0 dummy * 11 12 13 14 ios switch from input to output byte 1 byte 2 byte 3 *" set read parameters " command ( c 0 h ) can set the number of dummy clocks 7. 3 3 . enable qpi (38h) the device support both standard/dual/quad spi and qpi mode. the enable qpi (38h) command can switch the device from spi mode to qpi mode. see the command table 2a for all support qpi commands. in order to switch the device to qpi mode, the quad enable (qe) bit in status register-1 must be set to 1 first, and enable qpi (38h) command must be issued. if the qe bit is 0, the enable qpi (38h) command will be ignored and the device will remain in spi mode. when the device is switched from spi mode to qpi mode, the existing write enable latch and program/erase suspend status, and the wrap length setting will remain unchanged. figure 35. enable qpi mode command sequence diagram command 0 1 2 3 4 5 6 7 38 h cs # sclk si
48 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 7. 34 . disable qpi (ffh) to exit the qpi mode and return to standard/dual/quad spi mode, the disable qpi (ffh) command must be issued. when the device is switched from qpi mode to spi mode, the existing write enable latch and program/erase suspend status, and the wrap length setting will remain unchanged. figure 36. disable qpi mode command sequence diagram cs # sclk io 0 io 1 io 2 io 3 0 1 command ffh
49 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash figure 37a. enable reset and reset command sequence diagram (qpi) cs # sclk io 0 io 1 io 2 io 3 0 1 command 66 h 0 1 command 99 h 7. 35 . enable reset (66h) and reset (99h) if the reset command is accepted, any on-going internal operation will be terminated and the device will return to its default power-on state and lose all the current volatile settings, such as volatile status register bits, write enable latch status (wel), program/erase suspend status, read parameter setting (p7-p0), continuous read mode bit setting (m7-m0) and wrap bit setting (w6-w4). the enable reset (66h) and the reset (99h) commands can be issued in either spi or qpi mode. the reset (99h) command sequence as follow: cs# goes low sending enable reset command cs# goes high cs# goes low sending reset command cs# goes high. once the reset command is accepted by the device, the device will take approximately t rst =30 s to reset. during this period, no command will be accepted. data corruption may happen if there is an on-going or suspended internal erase or program operation when reset command sequence is accepted by the device. it is recommended to check the busy bit and the sus bit in status register before issuing the reset command sequence. figure 37. enable reset and reset command sequence diagram figure 38. enable reset and reset command sequence diagram 7.34. read serial flash discoverable parameter (5ah)
50 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 8.1 . power-on timing symbol parameter min max unit tvsl vcc(min) to cs# low 10 us tpuw time delay from vcc(min) to write instruction 1 10 ms vwi write inhibit voltage vcc(min) 1 1.4 v table 3. power-up timing and write inhibit threshold 8. electrical characteristics 8 . 2 . initial delivery state the device is delivered with the memory array erased: all bits are set to 1(each byte contains ffh). the status register contains 00h (all status register bits are 0). 8 . 3 . data retention and endurance parameter test condition min unit minimum pattern data retention time 150c 10 years 125c 2 0 years erase/program endurance -40 to 85c 100k cycles 8 . 4 . latch up characteristics parameter min max input voltage respect to vss on i/o pins -1.0v vcc+1.0v vcc current -100ma 100ma figure 38. power-on timing sequence diagram
51 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 8 . 5 . absolute maximum ratings parameter value unit ambient operating temperature -40 to 85 c storage temperature -55 to 1 25 c output short circuit current 200 ma applied input/output voltage -0.6 to vcc+0.4 v v cc -0.6 to vcc+ 0.4 v 8 . 6 . capacitance measurement conditions symbol parameter min typ max unit conditions cin input capacitance 6 pf vin=0v cout output capacitance 8 pf vout=0v c l load capacitance 30 pf input rise and fall time 5 ns input pulse voltage 0.2vcc to 0.8vcc v input timing reference voltage 0.3vcc to 0.7vcc v output timing reference voltage 0.5vcc v figure 39. input test wave form and measurement level 0 v - 0 . 6 v 20 ns 20 ns 2 . 35 v 1 . 95 v maximum negative overshoot waveform maximum positive overshoot waveform 0 v - 0 . 6 v 20 ns 20 ns 2 . 35 v 1 . 95 v maximum negative overshoot waveform maximum positive overshoot waveform 0 . 8 v c c 0 . 2 v c c 0 . 7 v c c 0 . 3 v c c 0 . 5 v c c a c m e a s u r e m e n t l e v e l i n p u t t i m i n g r e f e r e n c e l e v e l o u t p u t t i m i n g r e f e r e n c e l e v e l n o t e : i n p u t p u l s e r i s e a n d f a l l t i m e a r a < 5 n s
52 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 8. 7 . dc characteristics symbol parameter test condition min. typ. max. unit. i li input leakage current 2 a i l o output leakage current 2 a i cc1 standby current cs#=vcc, v in =vcc or vss 1 0 2 0 a i cc 2 deep power-down current cs#=vcc, v in =vcc or vss 1 5 a i cc 3 operating current (read) clk=0.1vcc/0.9vcc at 120mhz, q=open(*1,*2,*4 i/o) 15 20 ma clk=0.1vcc/0.9vcc at 80mhz, q=open(*1,*2,*4 i/o) 13 18 ma i cc 4 operating current (pp) cs#=vcc 2 5 ma i cc 5 operating current (wrsr) cs#=vcc 25 ma i cc 6 operating current (se) cs#=vcc 2 5 ma i cc 7 operating current (be) cs#=vcc 2 5 ma v i l input low voltage -0.5 0.3vcc v v i h input high voltage 0.7vcc vcc+0.4 v v ol output low voltage i ol =100 a 0.2 v v o h output high voltage i oh =-100 a vcc-0.2 v (t= -40 c ~85 c , vcc=1.65~1.95v )
53 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 8. 8 . ac characteristics symbol parameter min. typ. max. unit. f c serial clock frequency for: 0bh, 3bh, bbh, 6bh, ebh, e7h dc. 120 mhz f c serial clock frequency for: 0bh, 0ch, ebh with qpi mode (4 & 6 & 8 dummy clocks) dc. 80/120/120 mhz f r serial clock frequency for: read(03h) dc. 80 mhz t clh serial clock high time 4 ns t c ll serial clock low time 4 ns t clc h serial clock rise time (slew rate) 0.2 v/ns t chc l serial clock fall time (slew rate) 0.2 v/ns t slc h cs# active setup time 5 ns t chsh cs# active hold time 5 ns t s h ch cs# not active setup time 5 ns t c h sl cs# not active hold time 5 ns t shsl cs# high time (read/write) 20 ns t sh qz output disable time 6 ns t cl q x output hold time 1.2 ns t dvch data in setup time 2 ns t chdx data in hold time 2 ns t hlch hold# low setup time (relative to clock) 5 ns t hhch hold# high setup time (relative to clock) 5 ns t chhl hold# high hold time (relative to clock) 5 ns t chh h hold# low hold time (relative to clock) 5 ns t hl qz hold# low to high-z output 6 ns t h h q x hold# low to low-z output 6 ns t clq v clock low to output valid 7 ns t whsl write protect setup time before cs# low 20 ns t s hwl write protect hold time after cs# high 100 ns t dp cs# high to deep power-down mode 20 s t res1 cs# high to standby mode without electronic signature read 20 s t res 2 cs# high to standby mode with electronic signature read 20 s t sus cs# high to next command after suspend 20 s t w write status register cycle time 5 15 ms t pp page programming time 0.4 2.4 ms t se sector erase time 6 0 500 ms t be block erase time(32k bytes/64k bytes) 0.3/0.5 1.0 /1.2 s t ce chip erase time(GD25LQ40) 4 8 s (t= -40 c ~85 c , vcc=1.65~1.95v, c l =30pf)
54 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash figure 40. serial input timing sclk cs# si msb so high-z lsb tchsl tslch tdvch tchdx tshch tchsh tchcl tclch tshsl figure 41. output timing cs # sclk so si least significant address bit ( lib ) in tclqv tclqx tclqx tclqv tclh tcll tshqz lsb figure 42. hold timing cs # sclk so hold # tchhl thlqz thlch tchhh thhch thhqx si do not care during hold operation .
55 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash gd 25 lq 40 x i g x 9 . ordering information packing type y: tray r: tape & reel green code g: pb free & haloge n free green package temperature range i: industrial(-40 c to +85 c) package type t : sop8 150mil s : sop8 208mil n: uson8 (43mm) w: wson8 (6 5mm) density 4 0 : 4 mb series lq : 1.8 v , 4kb uniform sector product family 25 : s pi interface flash
56 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 10.1. package sop8 150mil 10 . package information 1 4 5 8 e1 e d a a2 a1 e b l l1 c ? seating plane 0. 10 symbol a a1 a2 b c d e e1 e l l1 ? unit mm min 1.35 0.05 1.35 0.31 0.15 4.77 5.80 3.80 - 0.40 0.85 0 6 11 nom - - - - - 4.90 6.00 3.90 1.27 - 1.06 - 7 12 max 1.75 0.25 1.55 0.51 0.25 5.03 6.20 4.00 - 0.90 1.27 8 8 13 inch min 0.053 0.002 0.053 0.012 0.006 0.188 0.228 0.149 - 0.016 0.033 0 6 11 nom - - - 0.016 - 0.193 0.236 0.154 0.050 0 0.042 - 7 12 max 0.069 0.010 0.061 0.020 0.010 0.198 0.244 0.158 - 0.035 0.050 8 8 13 dimensions note: both package length and width do not include mold flash.
57 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 10.2. package sop8 208mil 1 4 5 8 e1 e d a a2 a1 e b l l1 c ? symbol a a1 a2 b c d e e1 e l l1 unit mm min - 0.05 1.70 0.31 0.18 5.13 7.70 5.18 - 0.50 1.21 0 nom - 0.15 1.80 0.41 0.21 5.23 7.90 5.28 1.27 0.67 1.31 5 max 2.16 0.25 1.91 0.51 0.25 5.33 8.10 5.38 - 0.85 1.41 8 inch min - 0.002 0.067 0.012 0.007 0.202 0.303 0.204 - 0.020 0.048 0 nom - 0.006 0.071 0.016 0.008 0.206 0.311 0.208 0.050 0.026 0.052 5 max 0.085 0.010 0.075 0.020 0.010 0.210 0.319 0.212 - 0.033 0.056 8 dimensions note: both package length and width do not include mold flash.
58 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 10.3. package uson8 ( 4 3 mm) symbol a a1 a2 b d d1 e e1 e2 e y l unit mm min 0.50 0.00 - 0.25 2.90 0.10 3 .90 0.70 - 0.00 0.50 nom 0.55 - 0.15 0.30 3.00 0.25 4 .00 0.80 0.80bsc 0.80bsc - 0.60 max 0.60 0.05 - 0.35 3.10 0.40 4 .10 0.90 - 0.08 0.70 inch min 0.020 0.000 - 0.010 0.114 0.004 0 .153 0.027 - 0.000 0.020 nom 0.022 - 0.006 0.012 0.118 0.010 0.157 0.031 0.031bsc 0.031bsc - 0.024 max 0.024 0.002 - 0.014 0.122 0.016 0.161 0.035 - 0.003 0.028 dimensions note: 1. both package length and width do not include mold flash. 2. the exposed metal pad area on the bottom of the package is connected to device ground (gnd pin), so both floating and connecting gnd of exposed pad are also available. d e t o p v i e w d 1 e 1 b e b o t t o m v i e w l 1 a 2 a 1 a s i d e v i e w y e 1
59 r ev.1. 0 59 - http://www.elm-tech.com GD25LQ40xigx 1.8v uni form sector dual and quad serial flash 10.4 package wson8 ( 6 5 mm) symbol a a1 a2 b d d1 e e1 e y l unit mm min 0.70 - 0.19 0.35 5.90 3.25 4 .90 3 .85 - 0.00 0.50 nom 0.75 - 0.22 0.42 6.00 3.37 5 .00 3.97 1.27 bsc 0.04 0.60 max 0.80 0.05 0.25 0.48 6.10 3.50 5 .10 4.10 - 0.08 0.75 inch min 0.028 - 0.007 0.014 0.232 0.128 0.193 0.151 - 0.000 0.020 nom 0.030 - 0.009 0.016 0.236 0.133 0.197 0.156 0.05 bsc 0.001 0.024 max 0.032 0.002 0.010 0.019 0.240 0.138 0.201 0.161 - 0.003 0.030 dimensions note: 1. both package length and width do not include mold flash. 2. the exposed metal pad area on the bottom of the package is connected to device ground (gnd pin), so both floating and connecting gnd of exposed pad are also available. d e top view d1 e1 b e bottom view l 1 a2 a1 a side view y

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